171 lines
6.4 KiB
C
171 lines
6.4 KiB
C
#ifndef _PLATFORM_UART_H
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#define _PLATFORM_UART_H
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#include <stdint.h>
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#include <macro.h>
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// <Description> <[Doc Page]>
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// UART Base Addesses [141]
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#define UART_0_ADDR 0x10010000L
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#define UART_1_ADDR 0x10010000L
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// UART Control Register Offsets [142]
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#define UART_TXDATA_OFF 0x00 // Transmit data register
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#define UART_RXDATA_OFF 0x04 // Receive data register
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#define UART_TXCTRL_OFF 0x08 // Transmit control register
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#define UART_RXCTRL_OFF 0x0C // Receive control register
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#define UART_IE_OFF 0x10 // UART interrupt enable
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#define UART_IP_OFF 0x14 // UART interrupt pending
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#define UART_DIV_OFF 0x18 // Baud rate divisor
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#define UART_NUMBER 2
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#define DEFAULT_BAUD 115200
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// UART ids
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typedef enum {
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UART0 = 0,
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UART1 = 1,
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} uart_id;
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/* Transmit Data Register (txdata) [142]
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* Writing to the txdata register enqueues the character contained in the data
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* field to the transmit FIFO if the FIFO is able to accept new entries. Reading
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* from txdata returns the current value of the full flag and zero in the data
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* field. The full flag indicates whether the transmit FIFO is able to accept
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* new entries; when set, writes to data are ignored. A RISC‐V amoor.w
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* instruction can be used to both read the full status and attempt to enqueue
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* data, with a non-zero return value indicating the character was not accepted.
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*/
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struct S_PACKED uart_txdata_reg {
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uint32_t data:8;
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uint32_t reserved:23;
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uint32_t full:1;
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};
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static_assert((sizeof(struct uart_txdata_reg) == sizeof(uint32_t)),
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"uart_txdata_reg is not the right size");
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/* Receive Data Register (rxdata) [143]
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* Reading the rxdata register dequeues a character from the receive FIFO and
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* returns the value in the data field. The empty flag indicates if the receive
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* FIFO was empty; when set, the data field does not contain a valid character.
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* Writes to rxdata are ignored.
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*/
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struct S_PACKED uart_rxdata_reg {
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uint32_t data:8;
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uint32_t reserved:23;
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uint32_t empty:1;
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};
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static_assert((sizeof(struct uart_rxdata_reg) == sizeof(uint32_t)),
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"uart_rxdata_reg is not the right size");
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/* Transmit Control Register (txctrl) [143]
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* The read-write txctrl register controls the operation of the transmit channel.
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* The txen bit con- trols whether the Tx channel is active. When cleared,
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* transmission of Tx FIFO contents is suppressed, and the txd pin is driven
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* high. The nstop field specifies the number of stop bits: 0 for one stop bit
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* and 1 for two stop bits. The txcnt field specifies the threshold at which the
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* Tx FIFO watermark interrupt triggers. The txctrl register is reset to 0.
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*/
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struct S_PACKED uart_txctrl_reg {
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uint32_t txen:1;
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uint32_t nstop:1;
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uint32_t reserved0:14;
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uint32_t txcnt:3;
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uint32_t reserved1:13;
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};
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static_assert((sizeof(struct uart_txctrl_reg) == sizeof(uint32_t)),
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"uart_txctrl_reg is not the right size");
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/* Receive Control Register (rxctrl) [144]
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* The read-write rxctrl register controls the operation of the receive channel.
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* The rxen bit controls whether the Rx channel is active. When cleared, the
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* state of the rxd pin is ignored, and no characters will be enqueued into the
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* Rx FIFO. The rxcnt field specifies the threshold at which the Rx FIFO
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* watermark interrupt triggers. The rxctrl register is reset to 0. Characters
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* are enqueued when a zero (low) start bit is seen.
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*/
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struct S_PACKED uart_rxctrl_reg {
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uint32_t rxen:1;
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uint32_t reserved0:15;
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uint32_t rxcnt:3;
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uint32_t reserved1:13;
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};
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static_assert((sizeof(struct uart_rxctrl_reg) == sizeof(uint32_t)),
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"uart_rxctrl_reg is not the right size");
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/* Interrupt Registers (ip and ie) [144]
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* The ip register is a read-only register indicating the pending interrupt
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* conditions, and the read- write ie register controls which UART interrupts
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* are enabled. ie is reset to 0. The txwm condition becomes raised when the
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* number of entries in the transmit FIFO is strictly less than the count
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* specified by the txcnt field of the txctrl register. The pending bit is
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* cleared when sufficient entries have been enqueued to exceed the watermark.
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* The rxwm condition becomes raised when the number of entries in the receive
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* FIFO is strictly greater than the count specified by the rxcnt field of the
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* rxctrl register. The pending bit is cleared when sufficient entries have been
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* dequeued to fall below the watermark.
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*/
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struct S_PACKED uart_ie_reg {
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uint32_t txwm:1;
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uint32_t rxwm:1;
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uint32_t reserved:30;
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};
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static_assert((sizeof(struct uart_ie_reg) == sizeof(uint32_t)),
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"uart_ie_reg is not the right size");
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struct S_PACKED uart_ip_reg {
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uint32_t txwm:1;
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uint32_t rxwm:1;
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uint32_t reserved:30;
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};
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static_assert((sizeof(struct uart_ip_reg) == sizeof(uint32_t)),
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"uart_ip_reg is not the right size");
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/* Baud Rate Divisor Register (div) [145]
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* The read-write, div_width-bit div register specifies the divisor used by baud
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* rate generation for both Tx and Rx channels. The relationship between the
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* input clock and baud rate is given by the following formula: The input clock
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* is the bus clock pclk. The reset value of the register is set to div_init,
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* which is tuned to provide a 115200 baud output out of reset given the
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* expected frequency of pclk. Table 85 shows divisors for some common core
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* clock rates and commonly used baud rates. Note that the table shows the
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* divide ratios, which are one greater than the value stored in the div
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* register. The receive channel is sampled at 16× the baud rate, and a majority
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* vote over 3 neighboring bits is used to determine the received value. For
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* this reason, the divisor must be ≥16 for a receive channel.
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*/
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struct S_PACKED uart_div_reg {
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uint32_t div:16;
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uint32_t reserved:16;
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};
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static_assert((sizeof(struct uart_div_reg) == sizeof(uint32_t)),
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"uart_div_reg is not the right size");
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struct S_PACKED uart_memory_map {
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struct uart_txdata_reg txdata;
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struct uart_rxdata_reg rxdata;
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struct uart_txctrl_reg txctrl;
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struct uart_rxctrl_reg rxctrl;
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struct uart_ie_reg ie;
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struct uart_ip_reg ip;
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struct uart_div_reg div;
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};
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static_assert((sizeof(struct uart_memory_map) == sizeof(uint32_t[7])),
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"uart_memory_map is not the right size");
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int uart_set_baudrate(uart_id id, int baud);
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int uart_init(uart_id id, uint32_t baud, int stop_bits);
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void uart_tx_byte(uart_id id, unsigned char b);
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void uart_tx_full(uart_id id);
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void uart_tx_buf(uart_id id, unsigned char *buf, unsigned int size);
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#endif
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